[Libre-soc-dev] daily kan-ban update 25aug2020

Jacob Lifshay programmerjake at gmail.com
Tue Aug 25 18:07:21 BST 2020

On Tue, Aug 25, 2020, 09:48 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> the CR0/SO alterations needed shouuuld not conflict, nor are they related
> to the issue.  i.e. it was the main result value that was off.
> double checking the spec, mulld and divd both alter OV/32 SO _and_ CR0 (but
> not CA/32) and those are missing from the MulDivOutputData spec.

They're present:
class DivMulOutputData(IntegerData):
    regspec = [('INT', 'o', '0:63'),
               ('CR', 'cr_a', '0:3'),
               ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
               ('XER', 'xer_so', '32')]


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