[Libre-soc-dev] daily kan-ban update 25aug2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Aug 25 18:56:19 BST 2020

On Tuesday, August 25, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

They're present:
> class DivMulOutputData(IntegerData):
>     regspec = [('INT', 'o', '0:63'),
>                ('CR', 'cr_a', '0:3'),
>                ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
>                ('XER', 'xer_so', '32')]

ah good then i probably got that right. shiftrot i definitely didn't,
xer_so needed to be added.

extsw and cntlz in Logical modify CR0.  CR0 reads SO. therefore Logical
must have SO as input in order to successfully construct CR0.  therefore SO
needs to propagate right the way through the Logical pipeline stages and
into the output stage, where its journey ends.

it *doesn't* get connected to the CompUnit for storage back in the XER
regfile, and that means a new ospec is needed: one that is identical to
LogicalOutputData *except* xer_so is removed.

and now that i think about it the... no, DivMul can set OV/32 which *does*
change SO therefore DivMulOutputData remains the same.

you're good, jacob, i won't be making mods to DivMul :)


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the Libre-soc-dev mailing list