[Libre-soc-dev] daily kan-ban update 25aug2020

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Aug 25 17:48:19 BST 2020

On Tuesday, August 25, 2020, Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Tue, Aug 25, 2020, 07:08 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> > change of topic: jacob the DIV FSM is not producing correct output and
> > needs some high priority attention.  the incorrect output means i cannot
> > test anything on the FPGA because the DIV pipe is way too large.
> I'm planning on working on that today

thanks jacob.  i added an example test case at the top of the div unit test.

the CR0/SO alterations needed shouuuld not conflict, nor are they related
to the issue.  i.e. it was the main result value that was off.

double checking the spec, mulld and divd both alter OV/32 SO _and_ CR0 (but
not CA/32) and those are missing from the MulDivOutputData spec.

so just a heads-up, on that one, i may need to adjust the later pipeline
stages while you're looking at the middle ones.


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