[libre-riscv-dev] buffered pipeline
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Mar 15 22:44:48 GMT 2019
On Fri, Mar 15, 2019 at 4:58 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> On Fri, Mar 15, 2019, 02:31 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> > the removal of the manual creation of names would remove a lot of
> > cruft from the code, making it simpler and easier to read.
> stage.stage_input and stage.stage_output are not actually nmigen modules so
> I wasn't sure if the automatic naming would work properly.
interestingly i've noticed that converting to a nmigen module results
in the auto-generation not including the name of the member module as
part of the name, yet with python classes they are.
i've yet to fully work out what's going on, however i stopped looking
at the verilog quite some time ago and went over to yosys ilang
graphviz instead. it's much simpler.
> > self._data_valid = Signal()
> I want to explicitly have reset=0 as it is important. for other signals
> where I don't actually care about the reset value, i leave it out.
> self._data_valid = Signal(reset=0)
yeah i initially did that in a couple of places as well. then i
moved over to specifying "reset_less=True" for the places where the
reset is not important.
if you don't add that argument, nmigen *will* auto-generate code that
resets the value to zero on a reset signal, whether you like it or
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