[libre-riscv-dev] buffered pipeline

Jacob Lifshay programmerjake at gmail.com
Fri Mar 15 16:58:20 GMT 2019

On Fri, Mar 15, 2019, 02:31 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Fri, Mar 15, 2019 at 2:04 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> > > I greatly prefer to use something other than stb or strobe for the
> name as
> > > I find stb to be totally unintuitive and strobe to be somewhat
> unintuitive.
> > > i'm perfectly fine switching to ready and valid; if chisel uses
> > > ready/valid, it's widespread enough that I don't think anyone reading
> it
> > > for the first time will have trouble understanding it.
> >
> >  yeah i like it.  hmm, ready is the inversion of busy, that's ok
> > though.  will update the buffered version accordingly.
> oof.  that was slightly mind-bending, luckily it was straightforward
> and mundane.  i'm also a bit eye-glazed from writing an article for
> linuxjournal, 6000 words in 3 and a half hours non-stop... bleh :)
> i took the opportunity to split out two classes IOAckIn and IOAckOut,
> the reason for keeping them being that if the class names were the
> same (because the signals named ready and valid were the same), the
> opportunity to discern them with prefixes "p_" for "previous stage
> connection" and "n_" for "connected to next stage" would be lost.
> btw, jacob, i notice that in the class "Stage", you manually postfix
> the name of the StageInput.  in the manner in which you've created the
> layout, nmigen automatically creates a name prefix, using underscores,
> based on the name of the class instance member variable that the
> signal is in.
> this name filters through to the verilog output, automatically.
> so in the case of the Stage instance, which has a StageOutput instance
> member, when the signal named "sending" is created, it would be
> *automatically* named "output_sending".
> the removal of the manual creation of names would remove a lot of
> cruft from the code, making it simpler and easier to read.
stage.stage_input and stage.stage_output are not actually nmigen modules so
I wasn't sure if the automatic naming would work properly.

> also, reset=0 is the default, and the width defaults to 1 as well.
> thus, overall:
>         self._data_valid = Signal(1, name=name + "_data_valid", reset=0)
> can therefore be replaced with:
>         self._data_valid = Signal()
I want to explicitly have reset=0 as it is important. for other signals
where I don't actually care about the reset value, i leave it out.
self._data_valid = Signal(reset=0)

> that's it.  that's all that's needed.
> l.
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