[libre-riscv-dev] buffered pipeline

Jacob Lifshay programmerjake at gmail.com
Thu Mar 14 17:30:55 GMT 2019

On Thu, Mar 14, 2019, 04:01 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> btw jacob, "input" is a keyword and should be avoided as a member of a
> class.  a recommended convention would be i_data and o_data, which have the
> advantage of being of equal length, resulting in vertical alignment in
> similar codeblocks.
It doesn't cause any problems here since both:
- verilog supports escaped identifiers so you can use anything that doesn't
contain whitespace including keywords
- all signals don't have the plain name "input", the signals instead have a
name like "stage_input_sending" or "stage_input_data"

> l.
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