[libre-riscv-dev] buffered pipeline

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Mar 15 00:37:44 GMT 2019

On Thu, Mar 14, 2019 at 5:31 PM Jacob Lifshay <programmerjake at gmail.com> wrote:

> On Thu, Mar 14, 2019, 04:01 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> > btw jacob, "input" is a keyword and should be avoided as a member of a
> > class.  a recommended convention would be i_data and o_data, which have the
> > advantage of being of equal length, resulting in vertical alignment in
> > similar codeblocks.
> >
> It doesn't cause any problems here since both:
> - verilog supports escaped identifiers so you can use anything that doesn't
> contain whitespace including keywords
> - all signals don't have the plain name "input", the signals instead have a
> name like "stage_input_sending" or "stage_input_data"

 sorry, you misunderstand: the use of keywords *in python* as
variables is a practice that is to be avoided.  the translation to
verilog (verilog keywords) is indeed something that should also be
avoided, which hadn't occurred to me, that is separate and distinct
from not using python keywords as function names or variables.

 one reason is that they are highlighted by syntax colour-highlighting
as "special words", which is a major distraction during development,
as it triggers instant neural red flag pathways that then require time
to investigate.


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