[libre-riscv-dev] Wish to work on
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sat Mar 9 22:33:56 GMT 2019
daniel i did this, below, to keep the entry match line from going
beyond 80 chars. note that ematch is *not* actually stored in a
*signal*, it's a *PYTHON* local variable.
this can be done however you need to be quite careful, as if the
intermediate local python variable is used more than once, the
expression is *COPIED* and will create COPIES of the hardware which
will bleed through to the yosys graph.
although yosys has an optimiser phase when it comes to removing
duplicate expressions, the duplicates make the graphs harder to
understand, and make yosys work harder by being forced to identify
duplicates in the first place.
the obvious "fix" then is to assign to a Signal.... however in this
case it's not needed because ematch is used once and only once.
diff --git a/TLB/src/Cam.py b/TLB/src/Cam.py
index fcdecc2..de9be90 100644
@@ -91,8 +91,9 @@ class Cam():
# Send data input to all entries
m.d.comb += entry_array[index].data_in.eq(self.data_in)
- #Send all entry matches to encoder
- m.d.comb +=
+ # Send all entry matches to encoder
+ ematch = entry_array[index].match
+ m.d.comb += self.vector_assembler.i[index].eq(ematch)
On Sat, Mar 9, 2019 at 10:17 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> On Sat, Mar 9, 2019 at 9:21 PM Daniel Benusovich
> <flyingmonkeys1996 at gmail.com> wrote:
> > > I see, new modules: AddressEncoder, Decoder, VectorAssembler, etc have been added when i run read_verilog Cam.v
> > I added those yesterday to clean up the mess of lines that come after
> > the "anonymous" blocks that serve as CamEntry modules. If you ever add
> > a new sub module to a design you will see it populate that field.
> > Note that the some are anonymous and some are named.
> i think it might be possible to give the Array-anonymous thingies
> names by assigning a variable "name" to them. obj.name = "camentry%d"
> % idx
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