[libre-riscv-dev] CAM multiple match policy

Daniel Benusovich flyingmonkeys1996 at gmail.com
Tue Mar 5 08:43:18 GMT 2019

>  hurrah! :)  then that would be a usage bug.  as in, if a L1 or L2 or
> TLB has multiple matching entries, that's a really, really serious and
> critical fault that would require the processor to halt with extreme
> prejudice.
> Sounds good. I implemented the first part of the CAM following the
interface and have updated the tests for the most part. Its a bit late now
though so more tomorrow.

like a nmigen PriorityEncoder
Exactly what I was planning on using haha.

 think about it: what on earth would you do if that occurred?  which
> of the 2 (or more!) cache lines would you read (or write) the data to?
The only conceivable use I can think of is if you're pairing blocks of memory
> like  RAIR-1 drive.  In which case you'd read from either and write to both.
>       .-.
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l42 ==' '==

  one cycle goooood.

I agree!

 demand... respectfully:
> I would not plan on doing it any other way!

please, do leave it to me to deal with the Trademark issues....
> Understood. With Xilinx or going to the hw-dev mailing list?

As for the yosys I need to install it tomorrow and run the sucker so that
will be fun. The Make file will be broken for a bit as the interface is
implemented today and tomorrow.

Two read ports would be cool but I have a feeling it would be a very hungry

Anyways until tomorrow


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