[libre-riscv-dev] CAM multiple match policy
hendrik at topoi.pooq.com
Mon Mar 4 20:55:02 GMT 2019
On Mon, Mar 04, 2019 at 09:40:09AM +0000, Luke Kenneth Casson Leighton wrote:
> for a L1, L2 or TLB, multiple entries is a real serious and
> absolutely critical hard fault. there should *never*, under *any*
> circumstances, be a situation where two L1 cache lines match for a
> given address. EVER.
> think about it: what on earth would you do if that occurred? which
> of the 2 (or more!) cache lines would you read (or write) the data to?
The only conceivable use I can think of is if you're pairing blocks of memory
like RAIR-1 drive. In which case you'd read from either and write to both.
Yes, I think this is far-fetched.
More information about the libre-riscv-dev