[libre-riscv-dev] CAM multiple match policy
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Mon Mar 4 10:26:48 GMT 2019
btw daniel, code clarity looks absolutely great, comment strings are
clear and to the point, and the modules are the right kind of size to
be easily reviewable using yosys "show".
i added a Makefile which allows for compiling an example Cam.py to
verilog, then ran yosys "show" on it: attached so you can see what's
one thought: perhaps it *may* be necessary to have a 2R1W front-end: 2
read ports, 1 write port, i don't honestly know. it would mean
doubling the power consumption, which is a Bad Thing To Be Avoided.
anyway i wanted to put the graph by you, in case it encourages you to
think, "hmmmm...." :)
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