[libre-riscv-dev] CAM multiple match policy

Luke Kenneth Casson Leighton lkcl at lkcl.net
Tue Mar 5 09:09:08 GMT 2019

[editing and repairing the damaged thread context]

On Tue, Mar 5, 2019 at 8:43 AM Daniel Benusovich
<flyingmonkeys1996 at gmail.com> wrote:
> On some previous date, i wrote:
> >  hurrah! :)  then that would be a usage bug.  as in, if a L1 or L2 or
> > TLB has multiple matching entries, that's a really, really serious and
> > critical fault that would require the processor to halt with extreme
> > prejudice.
> >
> > Sounds good. I implemented the first part of the CAM following the
> interface and have updated the tests for the most part.


> Its a bit late now though so more tomorrow.

 no problem.

> > like a nmigen PriorityEncoder
> Exactly what I was planning on using haha.


> > please, do leave it to me to deal with the Trademark issues....
> >
>  Understood. With Xilinx or going to the hw-dev mailing list?

 neither.  with the RISC-V Foundation.

> As for the yosys I need to install it tomorrow and run the sucker so that
> will be fun.

 it also helps ensure that really glaring design errors are avoided,
such as this spectacular fail:


> The Make file will be broken for a bit as the interface is
> implemented today and tomorrow.
> Two read ports would be cool but I have a feeling it would be a very hungry
> hippo.

 and likely isn't needed.


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