[libre-riscv-dev] IEEE754 FPU

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Mar 4 04:16:34 GMT 2019

On Sun, Mar 3, 2019 at 2:46 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> Left shift done, right shift not yet because that needs the sticky bit merging thing, same trick with guard and round needed.

 right shift with sticky merge bit separated into module, now using it
in align.  also did a walkthrough video https://youtu.be/DsnoDN6NfmA
which covers identifying significant code-duplication (hidden behind
the innocuous use of a python / nmigen function), and shows how to get
rid of it.

 still todo, use right-shift-with-sticky-merge in normalisation.


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