[libre-riscv-dev] IEEE754 FPU

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Mar 3 02:46:00 GMT 2019

PriorityEncoder worked, someone on mlabs freenode irc told me they did a
verilog conversion that used one. Copied and adapted, mucked it up, fixed
it :)

The trick of reassembling the mantissa from the guard and round overflow
bits prior to shifting did the trick.

Left shift done, right shift not yet because that needs the sticky bit
merging thing, same trick with guard and round needed.


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

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