[libre-riscv-dev] IEEE754 FPU
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Tue Mar 5 02:55:52 GMT 2019
On Mon, Mar 4, 2019 at 4:16 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:
> still todo, use right-shift-with-sticky-merge in normalisation.
done. tested however the multi-shift code now needs an ACK/STB
system which i haven't added yet, and will fail to work until it is.
i've moved on now to adding in an id which propagates through the
stages. the reason for adding this is so that when there are a bank
of inputs and a bank of output buffers, each one may be allocated an
ID. the reason for doing *that* is because the pipelines can exit
early *or* even be a multi-cycle.
we need to be able to pass in, process, and receive multiple results,
regardless of how long each result takes, as that's part of the way
that an ALU is used as a Function Unit.
More information about the libre-riscv-dev