[libre-riscv-dev] TLB

Luke Kenneth Casson Leighton lkcl at lkcl.net
Sun Apr 21 19:17:15 BST 2019

On Monday, April 22, 2019, Jacob Lifshay <programmerjake at gmail.com> wrote:

> The privileged spec requires support for Sv39. We are planning on
> supporting Sv48 as well, rather than instead of Sv39.
> I think we were planning on supporting OmniXtend over the ethernet port,

I remember now, you mentioned it a couple months back.

Can you find this discussion on list archives and post a crossref to the
latest bugreport, mentioning omniextend for eval?

Also gen-z

which would allow supporting 500000 cores (or more) with appropriate
> ethernet switches, though at that scale we should think about
> error-correcting additions to the OmniXtend protocol, since it assumes
> (last I checked) that no messages are lost.
> OmniXtend supports both of the two most common cache coherence protocols:
> directory-based and snoop-based (as well as others), so we should be able
> to support most practical cache coherence designs.


Is there a L2 cache implementation already available?

And, how is OE accessed?

OpenPiton, the ariane team created an AXI4 adapter, and the OP team added
corresponding code.

Also there exists linux kernel source for OP.

If OmniExtend, being developed by WD, require closed secretive discussion
to find out how to use it, that's a black mark.

OpenPiton is developed by Princeton, they don't limit discussion or


crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

More information about the libre-riscv-dev mailing list