[libre-riscv-dev] TLB

Jacob Lifshay programmerjake at gmail.com
Sun Apr 21 18:50:40 BST 2019

The privileged spec requires support for Sv39. We are planning on
supporting Sv48 as well, rather than instead of Sv39.

I think we were planning on supporting OmniXtend over the ethernet port,
which would allow supporting 500000 cores (or more) with appropriate
ethernet switches, though at that scale we should think about
error-correcting additions to the OmniXtend protocol, since it assumes
(last I checked) that no messages are lost.

OmniXtend supports both of the two most common cache coherence protocols:
directory-based and snoop-based (as well as others), so we should be able
to support most practical cache coherence designs.

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