[libre-riscv-dev] pipeline sync issues
programmerjake at gmail.com
Fri Apr 12 06:45:58 BST 2019
On Thu, Apr 11, 2019 at 9:23 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Fri, Apr 12, 2019 at 4:51 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> > if the proposed Stage (merged) contains *any* sync'd logic on data,
> > ready or valid signals, it will *NOT* be possible to chain them
> > together and expect the output to be COMBINATORIALLY produced in a
> > SINGLE cycle.
> is that clear now?
Yeah. What you are calling Stage I was calling CombStage and what you were
calling Pipeline is most similar to what I was calling Stage. I had missed
that you want all Stage instances to be entirely combinatorial.
In my proposal, I'm thinking of switching the Stage/Pipeline naming to a
new naming scheme, to avoid confusion coming from semantics already
attached to those names.
> """A pipeline stage that delays by zero clock cycles and has
> ``pred.ready_out`` be the output of a flip-flop.
> this is untrue. buffer_full is set synchronously, and ready_out is
> assigned to ~buffer_full combinatorially. THEREFORE READY_OUT IS
Yeah, ready_out is synchronous. However, when ready_in and ready_out are
both set, then BreakReadyChainStage delays the data going through it by 0
clock cycles (I didn't write all the qualifications). RegStage is designed
to delay by 1 cycle when ready_in and ready_out are set. Both of them delay
data indefinitely while ready_in is not set.
> can you please acknowledge that you do - or do not - understand this?
Yeah, makes sense.
More information about the libre-riscv-dev