[libre-riscv-dev] pipeline sync issues

Luke Kenneth Casson Leighton lkcl at lkcl.net
Fri Apr 12 05:22:48 BST 2019

On Fri, Apr 12, 2019 at 4:51 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

>  if the proposed Stage (merged) contains *any* sync'd logic on data,
> ready or valid signals, it will *NOT* be possible to chain them
> together and expect the output to be COMBINATORIALLY produced in a
> SINGLE cycle.

 is that clear now?  if it is not clear, try creating a chain of e.g.
RegStages or BreakReadyChainStages, and measure the number of clock

 the only one that will still result in zero clock cycles is:
CombStage... because it is (as long as the process function is
combinatorial), pure combinatorial.

 this makes the assignment readyout-to-readyin and validout-to-validin
completely redundant (unnecessary), hence why StageChain does not even
bother to get involved with ready/valid *at all*.

 i believe this logical understanding flaw comes down to the
assumption that time may be removed from the equation.  the comment in
BreakReadyChainStage shows this flaw:

class BreakReadyChainStage:
    """A pipeline stage that delays by zero clock cycles and has
    ``pred.ready_out`` be the output of a flip-flop.

this is untrue.  buffer_full is set synchronously, and ready_out is
assigned to ~buffer_full combinatorially.  THEREFORE READY_OUT IS

can you please acknowledge that you do - or do not - understand this?


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