[libre-riscv-dev] barrel processor as I/O and DMA controller

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Apr 10 18:46:58 BST 2019

On Wed, Apr 10, 2019 at 6:31 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> also, the current design has 5 harts, so 1GHz would mean 200Mips per core,
> assuming no stalling.

ok cool.  so 4 instructions @ 50mhz, assuming 1ghz, which is pretty
challenging.  also would mean needing different clock domains,
50mhz-1ghz for the IO prcessor say, and, 100-800mhz for the OoO ones.


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