[libre-riscv-dev] pipeline sync issues
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Apr 10 09:22:45 BST 2019
On Wed, Apr 10, 2019 at 9:06 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> no, it's all taken into account because succ.valid_out is not a flip-flop,
> it's a non-synchronous combination of pred.valid_in and the internal state,
> therefore it doesn't have to be listed as an input in the truth table. The
> truth table only needs to have the current state of all internal registers
> and all inputs from the outside listed as inputs in the truth table. The
> internal state consists of the buf_full signal (ignoring the data path),
this confused me as well: buf_full (or its inverse) is stored in
p_o_ready. therefore p_o_ready *is* buf_full (or, its inverse).
therefore, when calculating the truth table, whenever buf_full occurs,
replace it with ~p_o_ready.
we can draw that conclusion from this:
m.d.comb += self.p._o_ready.eq(~buf_full)
if that was a "sync" it would be a different matter. however, it's a
"comb", therefore p_o_ready *is* ~buf_full. buf_full *is* ~p_o_ready.
so on all occurrences of buf_full, we can substitute (respecting the
inversion) and eliminate buf_full.
thus it is part of the synchronous state, and time (past-present)
does have to be taken into consideration.
i'll add a table for UnbufferedPipeline2 (based directly on BreakReadyStage).
More information about the libre-riscv-dev