[libre-riscv-dev] pipeline sync issues

Jacob Lifshay programmerjake at gmail.com
Wed Apr 10 09:05:51 BST 2019

On Wed, Apr 10, 2019, 00:52 Luke Kenneth Casson Leighton <lkcl at lkcl.net>

> On Wed, Apr 10, 2019 at 8:22 AM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> > One possible way to fix the truth table is to write in each row how many
> > data elements are stored in the stage and how many will be in the stage
> the
> > next clock cycle and make sure that that matches. This is similar to the
> > "transfer" column in
> >
> https://salsa.debian.org/Kazan-team/simple-barrel-processor/blob/master/doc/BreakReadyChainStage.rst
>  immediately, from the analysis i've done, i know that because it only
> has 8 states, it's invalid.  8 states means that one of the 4 pieces
> of information (i-v/r, o-v/r) is not being taken into account.
no, it's all taken into account because succ.valid_out is not a flip-flop,
it's a non-synchronous combination of pred.valid_in and the internal state,
therefore it doesn't have to be listed as an input in the truth table. The
truth table only needs to have the current state of all internal registers
and all inputs from the outside listed as inputs in the truth table. The
internal state consists of the buf_full signal (ignoring the data path),
whereas in BufferedPipeline the internal state includes p_o_ready and
n_o_valid because they are treated as flip-flops.

> > Once the truth table is fixed then you just have to change the nmigen
> code
> > to match.
> > >
> > > note: if we don't conform to the industry-standard practices for
> > > ready/valid, we will not be able to use SyncFIFO in our designs.
> > >
> > I haven't checked the api, but building adaptors should be quite simple.
>  ... it was.  w00t!
> https://git.libre-riscv.org/?p=ieee754fpu.git;a=blob;f=src/add/singlepipe.py;h=d7aee14d2dd3f4442def4c8449ee47dbc2539293;hb=fb8d2e66c4b263207d9990bdc542c46d6b37d48e#l919
> i ran a couple of manual tests, setting the FIFO depth to 2 and to
> 4... and it works!  amazing.

> l.
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