[libre-riscv-dev] need help with auto-pipeline stage creation
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Apr 3 09:28:35 BST 2019
On Wed, Apr 3, 2019 at 9:15 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> try printing the list of assignments and looking for the missing ones.
> __repr__() on Assign is overloaded to show what's being assigned where.
i've augmented signal's __repr__ to add the DUID: i'm still getting
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