[libre-riscv-dev] need help with auto-pipeline stage creation
programmerjake at gmail.com
Wed Apr 3 09:14:45 BST 2019
On Wed, Apr 3, 2019, 01:10 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> On Wed, Apr 3, 2019 at 7:26 AM Jacob Lifshay <programmerjake at gmail.com>
> > If something gets way too complex, I find reimplementing using the
> > implementation as reference usually helps.
> i'm not quite there yet, as i don't have an actual understanding of
> the issues in order to _begin_ a new implementation. i'm basically
> losing track of how the __getattr__ and __setattr_ overloads work in
> conjunction with the nmigen AST, which is itself based on overloads of
> arithmetic operators.
> the nmigen arithmetic operator overloads are used to accumulate an
> AST, which *normally* is passed in to an "m.d.sync +=
> signal.eq(something)" call.
> i am *delaying* that assignment into m.d.sync (or m.d.comb),
> accumulating the list of assignments and adding them to *modules*
> which are created dynamically - one per stage - as a way to create a
> unfortunately, somewhere along the line, the chain of assignments is
> broken, leaving inputs disconnected from outputs. i do not know where
> this is occurring.
try printing the list of assignments and looking for the missing ones.
__repr__() on Assign is overloaded to show what's being assigned where.
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