[Libre-soc-sim] Progress

[Peter Hsu]

If anyone interested in POWER port let me know, I am happy to help.  Otherwise I shall be (i) making multithreading work, and (ii) integrating pipeline timing simulator.  Goal is timing model of riscv shared bus multiprocessor running core-for-core on x86.

-Peter

> On Aug 14, 2021, at 8:47 PM, lkcl <luke.leighton at gmail.com> wrote:
> 
> 
> 
>> On August 14, 2021 5:47:49 PM UTC, Peter Hsu <peter.hsu at bsc.es> wrote:
>> Hello Luke, All,
>> 
>> riscv64-...-gdb seems to be working now.  Must compile programs with 
>> -fno-omit-frame-pointer to make backtrace work:
> 
> this is great news, having single-stepping, the possibility exists to use gdb machine interface to automatically run unit tests, single step them, and check the results.
> 
> we do that with qemu at the moment, it is possible to do side-by-side single step, compare a memdump and regdump after each instruction.
> 
> it is horribly slow but you can ensure comparative correctness of specific instruction implementations.
> 
> by running thousands of such programs we ironically found obscure bugs in qemu ppc64.
> 
> l.