[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #34 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #31)
> for comparison, fcmpo always writes to the destination since it is in a
> different register file and therefore can't be overwriting any inputs even
> when fcmpo causes an identical trap.

fcmpo does not provide a good precedent here to follow because it is not
a "co-result" instruction (not an Rc=1) it is a 5-bit instruction targetting
a specific CR-bit (not a CR-field bit)

fcmpo:

* reads two FPRs
* writes one bit to CR

these instructions are an *arithmetic* profile

* read one FPR
* write to one GPR *and a co-result CR0*

in other words, the issue you think is an issue is actually invalid.

this *is* doing the right thing:

    if vex_flag = 0 then
        RT <- result
        FPSCR.FPRF <- undefined(0b00000)
        FPSCR.FR <- inc_flag
        FPSCR.FI <- xx_flag
    else
        FPSCR.FR <- 0
        FPSCR.FI <- 0

RT *must not* be written to [in the pseudocode]
CR0 *must not* be written to [in the pseudocode]
writing to overflow *is* correct

there is no change required to the pseudocode.

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