[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #33 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #30)
> just leave it as this:
> 
>    v = fptoint(FRB)
>    if overflow and enabled:
>        trap()
>    else:
>        RT = v
> 
> * overflow will be written into CR0 by ISACaller (post-pseudocode-execution)
> * CR0's remaining bits are undefined (to be mentioned in the english language
>   spec section)
> * even if RT is analysed by ISACaller (post-pseudocode-execution) it is
>   "Not Your Problem(tm)" - because RT is undefined.

that's not how pseudocode works in the PowerISA spec, if it doesn't explicitly
write `undefined` to RT, then RT is not undefined. in this case RT is
unmodified.

plus, this doesn't match fcmpo, the only other kind of inter-regfile fp op with
traps i could find.

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