[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed May 24 11:39:59 BST 2023


--- Comment #35 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #33)

> that's not how pseudocode works in the PowerISA spec, if it doesn't
> explicitly write `undefined` to RT, then RT is not undefined. in this case
> RT is unmodified.

great. that's fine, good catch.  CR0 should still be UNDEFINED in all its 3
except overflow, with words to that effect written into the english language
part of the spec (not the pseudocode).

> plus, this doesn't match fcmpo, the only other kind of inter-regfile fp op
> with traps i could find.

as i said that is not an Rc=1 co-result instruction and comparing with
it is invalid.

action required:

* NONE (no change) on the pseudocode
* English language text stating "on exception CR0 fields UNDEFINED except

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