[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #29 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #27)
> (In reply to Jacob Lifshay from comment #23)
> > (In reply to Luke Kenneth Casson Leighton from comment #22)
> > > (In reply to Jacob Lifshay from comment #20)
> > > 
> > > jacob: i think you keep misunderstanding: RT *is* always written by
> > > the simulator.
> > 
> > i understand that perfectly fine, my proposal has nothing to do with how the
> > simulator works, it is to make the pseudocode always write to RT so hw
> > doesn't have to mask off writes to CR0 (causes problems for ddff) or read RT
> > from the regfile to compute CR0.
> 
> no you cannot do that, it entirely breaks how CR-field co-results work.

which part can i not do? the part with the current semantics which i thoroughly
dislike with reading RT? or the part with changing the pseudocode to always
write RT which I think is the best option overall?

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