[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #28 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #26)
> current semantics of fcvttgo.:
> v = fptoint(FRB)
> if overflow and enabled:
>     # do *not* modify RT
>     CR0 = compute_rc(RT)
>     trap()

no, really don't do that.  it should be this:

v = fptoint(FRB)

if overflow and enabled:
    CR0.SO = 1  CR.EQ/LT/GT = UNDEFINED
    trap()

actually, when overflow-bit is set, ISACaller already
spots that and already sets CR.SO.

and i think it reasonable to simply leave the rest of
the contents of CR0 completely alone (in the pseudocode)
and have english-language text stating "if overflow
all bits of CR0 except for CR0.SO are UNDEFINED"

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