[Libre-soc-isa] [Bug 1087] change ISACaller and correct bug introduced in parser.py where it bypasses FPSCR as a local parameter and a return result

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun May 21 21:16:00 BST 2023


--- Comment #13 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #12)
> e.g. fatan2s needs to be changed to something like:
> https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/
> fptrans.mdwn;h=e6799bb1a72767793330bfae70e5a17b6c6d6af5;
> hb=371d91b299c0e4bd7b23e660b9936ed40debb824#l14
> result <- DOUBLE(bfp32_ATAN2(SINGLE((FRA)), SINGLE((FRB))))
> if FPSCR.FEX = 0 then # computed as vex_flag in fcvt*

actually, rather than testing FEX, we need to test if *this instruction* sets
FEX (hence vex_flag), since FEX can be 1 on entry to the instruction (if MSR
exceptions are disabled or in non-precise exception modes)

>     FRT <- result
> else
>     # don't write FRT
>     # do other trap setup -- TBD
> ops like fmv don't need to change since they never cause fp traps.
> additionally, fcvt* might change to always write [F]RT (since that
> simplifies hardware and can't overwrite the input, unlike basically all
> other fp ops) but that change isn't technically necessary.

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