[Libre-soc-isa] [Bug 1087] change ISACaller and correct bug introduced in parser.py where it bypasses FPSCR as a local parameter and a return result

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #12 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> (In reply to Jacob Lifshay from comment #10)
> 
> > this bug is not motivated by how the simulator works, but by how the
> > PowerISA spec has decided to setup state in preparation for fp traps. we
> > need to match the PowerISA spec.
> 
> yes? and that's being done, yes? i see no difference between this
> (xscvdpsxds)
> 
<snip>
> 
> and this (fcvttg):
> 
<snip>
> 
> i see no difference between those in any way.

yes, because the places that we must change are all our other fp instructions
(fptrans, fft ops, etc.).

e.g. fatan2s needs to be changed to something like:
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isa/fptrans.mdwn;h=e6799bb1a72767793330bfae70e5a17b6c6d6af5;hb=371d91b299c0e4bd7b23e660b9936ed40debb824#l14

result <- DOUBLE(bfp32_ATAN2(SINGLE((FRA)), SINGLE((FRB))))
if FPSCR.FEX = 0 then # computed as vex_flag in fcvt*
    FRT <- result
else
    # don't write FRT
    # do other trap setup -- TBD

ops like fmv don't need to change since they never cause fp traps.

additionally, fcvt* might change to always write [F]RT (since that simplifies
hardware and can't overwrite the input, unlike basically all other fp ops) but
that change isn't technically necessary.

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