[Libre-soc-isa] [Bug 1087] change ISACaller and correct bug introduced in parser.py where it bypasses FPSCR as a local parameter and a return result

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sun May 21 20:49:44 BST 2023


--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #10)

> this bug is not motivated by how the simulator works, but by how the
> PowerISA spec has decided to setup state in preparation for fp traps. we
> need to match the PowerISA spec.

yes? and that's being done, yes? i see no difference between this

if vex_flag=0 then do
   VSR[32xTX+T].dword[1] <- result
   VSR[32xTX+T].dword[2] <- 0x0000_0000_0000_0000
   FPSCR.FR <- inc_flag
   FPSCR.FI <- xx_flag
else do
   FPSCR.FR <- 0b0
   FPSCR.FI <- 0b0

and this (fcvttg):

    vex_flag <- FPSCR.VE & vx_flag
    if vex_flag = 0 then
        RT <- result
        FPSCR.FPRF <- undefined(0b00000)
        FPSCR.FR <- inc_flag
        FPSCR.FI <- xx_flag
        FPSCR.FR <- 0
        FPSCR.FI <- 0

i see no difference between those in any way.

> the simulator must be adjusted to match
> pre-existing convention, 

yes? and i have not seen anything that needs to be changed *to* match?

> not convention adjusted to match our arbitrary
> simulator internals.

agreed... so what precisely and exactly are you envisioning needs to "change"?

you have not shown me where anything is that actually *needs to change*

> please confirm you understand that we need to solve the issue of getting the
> right pseudocode for the spec to match existing conventions,

i see neither an error in the pseudocode nor anything that needs to
change in the simulator to support a change that i cannot see is even

> please *don't repurpose bugs* like this, open a new bug and close the old
> one instead. it is especially problematic when the original bug is still a
> bug that needs fixing (like in this case),

i see no bug.

you need to tell me *precisely and exactly* what change is needed, and
where.  at present as i literally see no difference in the pseudocode
i am completely unable to understand why there is any change in the
simulator's behaviour needed.

> change this bug's title back to "change pseudocode to prevent output
> register write only when causing a fp trap and output is in same regfile as
> input" or at least "add pseudocode to properly setup for fp traps according
> to PowerISA spec convention"

sorry, i'm not doing that until - unless - you can demonstrate that there
is an actual change needed.

i cannot see any functional difference between the two pieces of text, above.
the only difference i see is the register target VSR instead of RT and that
is immaterial.

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