[Libre-soc-isa] [Bug 1087] change ISACaller and correct bug introduced in parser.py where it bypasses FPSCR as a local parameter and a return result

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #12)

> yes, because the places that we must change are all our other fp
> instructions (fptrans, fft ops, etc.).

ah ok.  so given that the places that *are* in the right pattern
(the if FEX then FRT/FPSCR else FPSCR parts) require no change
to the simulator, and that *works* right now (does the right
thing and requires - required - no change), i still do not see
why any change would be needed once all of those instructions
are modified to follow the exact same pattern

> e.g. fatan2s needs to be changed to something like:
>
> result <- DOUBLE(bfp32_ATAN2(SINGLE((FRA)), SINGLE((FRB))))
> if FPSCR.FEX = 0 then # computed as vex_flag in fcvt*
>     FRT <- result
> else
>     # don't write FRT
>     # do other trap setup -- TBD

where i assume by "do other trap setup" you mean "modify FPSCR flags
just like in the other locations"?

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