[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #0)
> https://libre-soc.org/irclog/%23libre-soc.2023-05-21.log.html#t2023-05-21T10:
> 29:37
> 
> things like fcvtfg don't need to prevent writing the output since the output
> is in a different regfile and thus can't possibly overlap with the input reg.

this is a misunderstanding of how the simulator works. a register that
requires writing *is* a local variable, *is* a return result from the
function.

    def op_fcvtfg(self, RB, FPSCR):
        if eq(IT[0], 0):
            FRT = copy_assign_rhs(result)
        return (FRT, FPSCR,)

> things like fsinpi f3, f3 need to prevent writing the output reg when they
> trap so the trap can see what the input was.

this is automatic and inherent.  the write of the results *is* automatically
inherently 100% without fail absolute without fail prevented.

there is no other choice.  declaring this bugreport invalid as there is
no change required (and no change ever going to happen) and it was raised
based on a misunderstanding.

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