[Libre-soc-isa] [Bug 1087] change pseudocode to prevent output register write only when causing a fp trap and output is in same regfile as input

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1087

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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                 CC|                            |lkcl at lkcl.net

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #1)
> basically we need to add/remove the pseudocode that explicitly sets up
> register state (FRT/RT and FPSCR, not SRR0 or other trap machinery) for
> taking a fp trap.
> see xscvdpsxds for an example -- we need to add/remove the `if vex_flag`

i have absolutely no idea why on earth that would be necessary.

can you please confirm that you understand that there is not and will never be
a change to action what you have recommended?  and that you understand
that FRT is a *local* variable returned as a *local* result, where ISACaller
has control *after* the pseudocode function is called as to whether the
result is written to the regfile?

what you should *not* have done is bypass the mechanism that was established
2 years ago for passing in registers and returning them

        if name in ('XLEN', 'FPSCR') or name in BFP_FLAG_NAMES:
            attr = ast.Name("self", ast.Load())
            p[0] = ast.Attribute(attr, name, ast.Load(), lineno=p.lineno(1))

that is *NOT* the correct behaviour.

look at the pseudocode

    def op_fcvttg_(self, FRB, ****>>>>> FPSCR <<<<<<*****):

        if eq(vex_flag, 0):
            RT = copy_assign_rhs(result)
            >>> NO! self. <<<< FPSCR.FPRF = copy_assign_rhs(self.undefined(
                SelectableInt(value=0x0, bits=5)))

        return (RT, *****>>>>> FPSCR <<<<<*****, overflow,)

you should *NOT* have attempted to bypass FPSCR being passed in as
a local variable, bypassed FPSCR as a return result.

updating of FPSCR goes into *check_write()*

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