[Libre-soc-isa] [Bug 1080] allowing LD/ST-Update to select individual regsters needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1080

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)

> the standard name is extractelement or extract
> https://llvm.org/docs/LangRef.html#extractelement-instruction
> 
> imho

(please do drop that, it's an affectation that gets tiring. we don't need
to know that your opinion is "humble" - here we just need to know what your
[valued] insights are, as third-person-objective constructive input.
also please trim)

> it may be more efficient to simply add r3 to the load address and
> perform a scalar load (optionally SVP64 prefixed) rather than setting
> sm=1<<r3, since that's much simpler and simple hardware then won't issue VL
> load ops for only one of them to succeed.

ta-daaa, now you're getting it.  and that's an optimisation that would
be performed by hardware that chose to implement micro-coding (which does
*not* mean "like intel does it", it just means "some form of rewriting"
rather than "straight naive 1:1". microwatt does micro-coding into OP_ADD)

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