[Libre-soc-isa] [Bug 1080] allowing LD/ST-Update to select individual regsters needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1080

--- Comment #5 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #4)
> (In reply to Luke Kenneth Casson Leighton from comment #3)
> > (In reply to Jacob Lifshay from comment #2)
> > > (In reply to Luke Kenneth Casson Leighton from comment #1)
> > > > (In reply to Luke Kenneth Casson Leighton from comment #0)
> > > > 
> > > > > lwzux,LDST_IDX,,2P,EXTRA2,EN,d:RT,d:RA,s:RB,0,RA_OR_ZERO,RB,0,RT,0,0,RA
> > > > > stdux,LDST_IDX,,2P,EXTRA2,EN,d:RA,s:RS;s:RA,s:RB,0,RA_OR_ZERO,RB,RS,0,0,0,RA
> > > > > 
> > > > > these become harder as the encoding space is only 6 bits (and there
> > > > > are 3 regs, RT/RS RA RB) due to Twin-Predication taking up 3 bits
> > > > > of EXTRA
> > > > 
> > > > this cannot be lost as it destroys VSPLAT VINDEX VGATHER VSCATTER
> > > 
> > > please define VINDEX 
> > 
> > sm=1<<r3. or just sm=r3 where one bit is set. there is probably another
> > name for it.
> 
> the standard name is extractelement or extract
> https://llvm.org/docs/LangRef.html#extractelement-instruction
> 
> imho it may be more efficient to simply add r3 to the load address and
> perform a scalar load (optionally SVP64 prefixed) rather than setting
> sm=1<<r3, since that's much simpler and simple hardware then won't issue VL
> load ops for only one of them to succeed.
> 
> extractelement is only really useful when extracting from a vector already
> in registers, since you can't always just add to the address for that.

oh, and insert or insertelement for the other way:
https://llvm.org/docs/LangRef.html#insertelement-instruction

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