[Libre-soc-isa] [Bug 1080] allowing LD/ST-Update to select individual regsters needed

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1080

--- Comment #7 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #6)
> (In reply to Jacob Lifshay from comment #4)
> > it may be more efficient to simply add r3 to the load address and
> > perform a scalar load (optionally SVP64 prefixed) rather than setting
> > sm=1<<r3, since that's much simpler and simple hardware then won't issue VL
> > load ops for only one of them to succeed.
> 
> ta-daaa, now you're getting it.  and that's an optimisation that would
> be performed by hardware that chose to implement micro-coding (which does
> *not* mean "like intel does it", it just means "some form of rewriting"
> rather than "straight naive 1:1". microwatt does micro-coding into OP_ADD)

umm, you seem to have missed my point which is that programmers should write a
scalar load instruction (sv.ldx r4, r5, r3) rather than sv.ld/sm=1<<r3 r4,
0(r5) since simple cpus won't perform that optimization since that's more
complex to do.

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