[Libre-soc-isa] ternlog & grevlut again -- was: next ISA WG RFC

[Jacob Lifshay]

On Mon, Mar 6, 2023, 11:25 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> ---
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
>
> On Mon, Mar 6, 2023 at 7:19 PM Jacob Lifshay <programmerjake at gmail.com>
> wrote:
> > the extra logic would go in the ternlog ALU, not the decoder.
>
> no, because illegal instruction (for "redundant" encodings)
> needs to be raised at the decode phase.
>

no, because the idea was to use 1 less immediate bit by excluding some
redundant encodings and coming up with some scheme to squish the immediate.
this wouldn't introduce any illegal instructions in ternlog's encoding
space but would instead make ternlog use half the encoding space:

e.g.:
ternlogi rt, ra, rb, rc, 8-bit-imm
rt = ternlog(ra, rb, rc, 8-bit-imm)
becomes:
ternlogi rt, ra, rb, rc, 7-bit-imm
rt = ternlog(ra, rb, rc, expand-encoded-imm(7-bit-imm))
# decoding still easy, uses contiguous block of encodings, no holes.
# expand-encoded-imm happens in ALU and doesn't affect insn decoding.
# no 7-bit-imm immediates are illegal.
# one downside is expand-encoded-imm may be complex or impossible -- tbd

this is *not* what I'm proposing:
ternlogi rt, ra, rb, rc, 8-bit-imm-except-not-ternlog-if-starts-with-0x7
# leaves hole in middle that we can shove new insns into, makes decoding a
pain

Jacob
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