[Libre-soc-isa] ternlog & grevlut again -- was: next ISA WG RFC

[Jacob Lifshay]

On Mon, Mar 6, 2023 at 11:40 AM Jacob Lifshay <programmerjake at gmail.com> wrote:
> no, because the idea was to use 1 less immediate bit by excluding some redundant encodings and coming up with some scheme to squish the immediate. this wouldn't introduce any illegal instructions in ternlog's encoding space but would instead make ternlog use half the encoding space:
>
> e.g.:
> ternlogi rt, ra, rb, rc, 8-bit-imm
> rt = ternlog(ra, rb, rc, 8-bit-imm)
> becomes:
> ternlogi rt, ra, rb, rc, 7-bit-imm
> rt = ternlog(ra, rb, rc, expand-encoded-imm(7-bit-imm))
> # decoding still easy, uses contiguous block of encodings, no holes.
> # expand-encoded-imm happens in ALU and doesn't affect insn decoding.
> # no 7-bit-imm immediates are illegal.
> # one downside is expand-encoded-imm may be complex or impossible -- tbd

found a function that afaict only needs 9 xor gates:
https://bugs.libre-soc.org/show_bug.cgi?id=745#c65

Jacob