[Libre-soc-isa] ternlog & grevlut again -- was: next ISA WG RFC

Luke Kenneth Casson Leighton lkcl at lkcl.net
Mon Mar 6 19:25:33 GMT 2023


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On Mon, Mar 6, 2023 at 7:19 PM Jacob Lifshay <programmerjake at gmail.com> wrote:
> the extra logic would go in the ternlog ALU, not the decoder.

no, because illegal instruction (for "redundant" encodings)
needs to be raised at the decode phase.

more later.

l.



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