[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Jun 8 05:53:46 BST 2023


--- Comment #71 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #70)
> which eliminates simple implementations (treating the two as separate
> instructions), they *have* to prohibit interrupts if reading only
> one 32-bit word per clock cycle. slightly annoying but not the end of
> the world.

they can still be treated as separate instructions, the cpu just has to disable
all interrupts and single-stepping between them, as well as counting
differently with performance counters.

x86 does a similar thing for the mov ss, reg instruction (move to stack segment

> Loading the SS register with a MOV instruction suppresses or inhibits some debug
> exceptions and inhibits interrupts on the following instruction boundary.
> (The inhibition ends after delivery of an exception or the execution of the
> next instruction.) This behavior allows a stack pointer to be loaded into the
> ESP register with the next instruction (MOV ESP, stack-pointer value) before an
> event can be delivered.

(luke, have we defined how SVP64 instructions interact with performance
counters around what counts as an instruction? e.g. when VL=5, does
sv.add *r3, *r30, r0
count as 1 instruction, 5 instructions, 6 instructions, implementation-specific
number of instructions, or something else?)

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