[Libre-soc-isa] [Bug 1056] questions and feedback (v2) on OPF RFC ls010

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1056

--- Comment #72 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #71)

> x86 does a similar thing for the mov ss, reg instruction (move to stack
> segment selector):
> https://www.felixcloutier.com/x86/mov

oooOoo :}

"Loading the SS register with a MOV instruction suppresses or inhibits some
debug
exceptions and inhibits interrupts on the following instruction boundary.
(The inhibition ends after delivery of an exception or the execution of the
next instruction.)"

oo this is good wording.

prompted me to look up rep again
https://www.felixcloutier.com/x86/rep:repe:repz:repne:repnz

and now i know what to look for, the rep prefix allows interrupts
in between but does *precisely* the same kind of "register" decrementing
that SVSTATE.srcstep (etc) is.

> (luke, have we defined how SVP64 instructions interact with performance
> counters around what counts as an instruction? e.g. when VL=5, does
> sv.add *r3, *r30, r0
> count as 1 instruction, 5 instructions, 6 instructions,
> implementation-specific number of instructions, or something else?)

sigh no, yet another thing on the todo list. good catch

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