[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1092

--- Comment #18 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://libre-soc.org/openpower/sv/normal/

| 0-1    |  2  |  3   4  |  description                     |
| ------ | --- |---------|----------------------------------|
| 0   0  |   0 |  dz  sz | simple mode                      |
| 0   0  |   1 |  RG  0  | scalar reduce mode (mapreduce)   |
| 0   0  |   1 |  /   1  | reserved                         |
| 1   0  |   N | dz   sz |  sat mode: N=0/1 u/s             |
| VLi 1  | inv | CR-bit  | Rc=1: ffirst CR sel              |
| VLi 1  | inv | zz RC1  | Rc=0: ffirst z/nonz              |

there's room in that (just) for a bit that says
"immediates are Vectorised".  ok: using mode[4]
says "immediates are Vectorised".

that still leaves mode[3] for some sort of decision.

the neat thing about this is that even sv.addi can load
an array of immediates.  oris as well.

as we discussed yesterday it requires an "Unconditional
Branch" effect, and i'd recommend it be on MAXVL not VL.
also to round-up to the nearest 4-bytes.

if RM."immediate-mode":

    NIA = CIA + CEIL(MAXVL * sizeof(immediate), 4)

jacob you mentioned during the meeting that this would
be "slow" i.e. dependent on Architectural State (SVSTATE),
if someone modified SVSTATE with mtspr then things get
slow: this is *already* in the spec.

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