[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1092

--- Comment #17 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #14)

> > elwidth=FP16/FB16 has to be taken into consideration.
> 
> that can be done with:
> addi r3, 0, 0x1234
> sv.fmtg/w=f16 *f5, r3

that's 3x 32-bit words instead of 2x 32-bit words,
for both SVP64 and SVP64Single (and it wastes a GPR).

how can elwidth=FP16/BF16 be supported *by fmi*.
(including SVP64Single/fmi)

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