[Libre-soc-isa] [Bug 1092] OPF RFC ISA WG questions feedback on ls002 float-load-immediate

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Sat Jun 10 02:06:43 BST 2023


--- Comment #19 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #15)

> alternatively fmi could be a 64-bit scalar instruction with a 32-bit
> immediate

given that:

* the process for justifying 64-bit instructions (EXT1xx) is very hard
* to add this proposal it would be necessary to squeeze scalar
  (Unvectorized) into PO9
* that is more than PO9 can bear (already close to the encoding limit)
* multi-issue, remember: the Apple M1 sustains 100% because all
  instructions are 32-bit.

we have to find another way.

i would be fine with fli2 being a "shift and append", and even reducing
down to just the one instruction fli where if FRA=0 it causes a
reset (clearing) of FRT.

    prevstuff <- (FRA|0)
    FRT <- prevstuff << 16 || imm

and be done with it.

repeated calls DoTheRightThing.  does this sound sane?

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