[Libre-soc-isa] [Bug 1071] maybe add parallel prefix sum remap mode

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=1071

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> how is it different from parallel prefix reduction bug #864?
> 
> https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/
> decoder/isa/remap_preduce_yield.py;hb=HEAD

parallel reduction is a reduction aka has only one output, the rest of the
output vector is intermediate results that aren't a prefix-sum. parallel
reduction is basically 1/2 a prefix-sum operation.

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