[Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=924

--- Comment #14 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #13)

> what i'm saying is bits 32:33 (34 is a typo)

yes, good catch

> should be changed to where zero
> indicates new svp64-scalar, and nonzero indicates reserved. right now you
> picked 11 indicates new svp64-scalar:
> https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls001.
> mdwn;h=16bcb16307a163e0f5d2483d4a7df84eba926720;
> hb=7a316cb8c159ba507a6278dea2f0b29d2d4a0fe3#l668

ah no. you've very much misunderstood.

bits 32-33 deliberately overlap with Primary Opcodes numbered 48 thru 63
(0b**11**0000 to 0b**11**1111).

bit 7 is responsible for differentiating between SVP64(Vector) and
SVP64(Single).

-- 
You are receiving this mail because:
You are on the CC list for the bug.