[Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=924

--- Comment #13 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #12)
> (In reply to Jacob Lifshay from comment #11)
> 
> > should still be able to do the bit 32:33 part afaict...
> 
> yes that's new.
> <snip>
> which then leaves 75% of 50% left for future ISA WG needs, a grand
> total of:
> 
> * 64 minus (
>   * 6-bit PO EXT009 (taken up)
>   * 1-bit "new" encoding (bit6)
>   * 2-bit "not SVP64-Reserved" (bits 32-34)

what i'm saying is bits 32:33 (34 is a typo) should be changed to where zero
indicates new svp64-scalar, and nonzero indicates reserved. right now you
picked 11 indicates new svp64-scalar:
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls001.mdwn;h=16bcb16307a163e0f5d2483d4a7df84eba926720;hb=7a316cb8c159ba507a6278dea2f0b29d2d4a0fe3#l668

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